1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor memory device including memory cells of the cross-point type, and a semiconductor memory device.
2. Description of the Related Art
Electrically erasable programmable nonvolatile memories include a flash memory as well known in the art, which comprises a memory cell array of NAND-connected or NOR-connected memory cells having a floating gate structure. A ferroelectric memory is also known as a nonvolatile fast random access memory.
On the other hand, technologies of processing memory cells much finer include a resistance variable memory, which uses a variable resistive element in a memory cell as proposed. Specifically, known examples include a phase change memory device that varies the resistance in accordance with the variation in crystal/amorphous states of a chalcogenide compound; an MRAM device that uses a variation in resistance due to the tunnel magneto-resistance effect; a polymer ferroelectric RAM (PFRAM) memory device including resistive elements formed of a conductive polymer; and an ReRAM device that causes a variation in resistance on electrical pulse application (Patent Document 1: JP 2006-344349A).
The resistance variable memory may configure a memory cell with a serial circuit of a Schottky diode and a resistance variable element in place of the transistor. Accordingly, it can be stacked easier and three-dimensionally structured to achieve much higher integration as an advantage (Patent Document 2: JP 2005-522045A).
Such the memory cells of the cross-point type may be manufactured as aligned with line patterns through a self-aligned process. In this case, first, processing trenches extending in a first direction with a certain line-and-space (hereinafter referred to as “L/S”) is applied to a stacked body including a lower wiring layer and a memory cell layer stacked thereon to form a plurality of first trenches, thereby separating the stacked body by the first trenches. Thereafter, an interlayer insulator film of SiO2 is buried in the first trenches, and an upper wiring layer is formed thereon. Then, processing trenches extending in a second direction orthogonal to the first direction with a certain L/S is applied to the upper wiring layer and the stacked body with the interlayer insulator film buried therein to form a plurality of second trenches reaching the upper surface of the lower wiring layer in depth, thereby forming the memory cells of the cross-point type between mutually orthogonal lines.
In the above-described manufacturing process, however, it is difficult to achieve a selection ratio of 1:1 between the material for forming the memory cell layer and SiO2 for forming the interlayer insulator film. Therefore, at the time of forming the second trenches, etching advances in the memory cell layer more than the interlayer insulator film. As a result, the residual interlayer insulator film serves as a mask to leave the residue of the memory cell material beneath the side wall of the interlayer insulator film, which may possibly cause a short between adjacent memory cells as a problem.